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With the switch to DDR2, AMD runs up against a problem: DDR2-800 has a clock speed of 400 MHz and can therefore no longer be divided by all previously envisaged CPU clock speeds. And the highest speed possible is not divisible by 400.

But how does the CPU react if a memory timing is set which cannot be divided by the CPU clock speed?

AMD came up with something smart here: if a divider is produced that exceeds the next possible JEDEC-compliant standard memory clock (400, 533, 667, 800), the next lower divider is selected automatically.

Athlon 64 X2 4800+: 2400 MHz / 6 = 400 MHz (DDR2-800)


Athlon 64 X2 4000+: 2000 MHz / 5 = 400 MHz (DDR2-800)
Athlon 64 X2 5000+: 2600 MHz / 7 = 371 MHz (DDR2-742)
Athlon 64 X2 4400+: 2200 MHz / 6 = 366 MHz (DDR2-733)

This produces highly curious memory clocks like DDR2-742 and DDR2-733. The automatic selection of the divider cannot be deactivated or influenced.

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