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if one checks the completed listings one can see the prices ranging from $110 to $170 :)

also processors that are overclocked wont just give way in a year, im sure you must have an old OCed CPU that you are still using? sam, is your E4300 still OCed?
by the time it could have given up, im sure we could have gone through 2/3 different processors.

creaky, IMO you are being unfair on boozer. he has backed up all his points, and yet you accuse him of not talking like an adult,

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Originally posted by sammorris:

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I spotted the 9600, but I think it was Russ that said you're likely to end up with one of those that still has the bug, or suffers degraded performance from how it was fixed, not sure which. Thing is, how far does the multiplier go, and how far will the CPU go?

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Originally posted by sammorris:

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Ok, thanks Russ. Yeah, I think I too will pass on recommending those to anyone. The 9650 is the first chip I'd go for, which by my last check was $155 at newegg. Not a great saving on the Q6600's 190, but every little helps I suppose.

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Originally posted by Sophocles:

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I'm going to recommend them without reservation. There are over 400 comments at Newegg and they are largely favorable. I don't know where you got your warranty info but according to what I read at newegg they have a 3 year warranty.

http://www.newegg.com/Product/Product.aspx?Item=N82E16819103244

Every processor that you purchase has some errors which is referred to as errata, but few of us ever notice them. The TLB bug is also errata.

http://download.intel.com/design/processor/specupdt/318733.pdf


There is also a TLB patch if it irritates one to know that they have it but for most real word applications the TLB amounts to nothing. The patch also lowers the performance a bit. When Donald gets his in I will provide more info but for those of you who knows Donald you also know that he is no fool when it comes to making a purchase.

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The "TLB Bug" Explained

Phenom is a monolithic quad core design, each of the four cores has its own internal L2 cache and the die has a single L3 cache that all of the cores share. As programs are run, instructions and data are taken into the L2 cache, but page table entries are also cached.

Virtual memory translation is commonplace in all modern OSes, the premise is simple: each application thinks it has contiguous access to all memory locations so they don't have to worry about complex memory management. When an application attempts to load or store something in memory, the address it thinks it's accessing is simply a virtual address - the actual location in memory can be something very different.

The OS stores a table of all of these mappings from virtual to physical addresses, the CPU can cache frequently used mappings so memory accesses take place much quicker.

If the CPU didn't cache page table entries, each memory access would proceed as follows:

1) Read from a pagetable directory
2) Read a pagetable entry
3) Then read the translated address and access memory

Then there's something called a Translation Lookaside Buffer (TLB) which takes the addresses and maps them one to one, so you don't even need to perform a cache lookup - there's just a direct translation stored in the TLB. The TLB is much smaller than the cache so you can't store too many items in the TLB, but the benefit is that with a good TLB algorithm you can get good hit rates within your TLB. If the mapping isn't contained in the TLB then you have to do a lookup in cache, and if it's not there then you have to go out to main memory to figure out the actual memory address you want to access.

Page table entries eventually have to be updated, for example there are situations when the OS decides to move a set of data to another physical location so all of the virtual addresses need to be updated to reflect the new address.

When page table entries are updated the cached entries stored in a core's L2 cache also need to be updated. Page table entries are a special case in the L2, not only does the cache controller have to modify the data in the entries to reflect their new values, but it also needs to set a couple of status bits in the page table entries in order to mark that the data has been modified.

Page table entries in cache are very different than normal data. With normal data you simply modify it and your cache coherency algorithms take care of making sure everything knows that the data is modified. With page table entries the cache controller must manually mark it by setting access and dirty bits because page tables and TLBs are actually managed by the OS. The cache line has to be modified, have a couple of bits set and then put back into the cache - an exception to the standard operating procedure. And herein lies the infamous TLB erratum.

When a page table entry is modified, the core's cache controller is supposed to take the cached entry, place it in a register, modify it and then put it back in the cache. However there is a corner case whereby if the core is in the middle of making this modification and about to set the access/dirty bits and some other activity goes into the cache, hits the same index that the page table entry is stored in and if the page table entry is marked as the next thing to be evicted, then the data will be evicted from the L2 cache and put into the L3 cache in the middle of this modification process. The line that's evicted from L2 is without its access and dirty bits set and now in L3, and technically incorrect.

Now the update operation is still taking place and when it finishes setting the appropriate bits, the same page table data will be placed into the core's L2 cache again. Now the L2 and L3 cache have the same data, which shouldn't happen given AMD's exclusive cache hierarchy.

If the line in L2 gets evicted once more, it'll be sent off to the L3 and there will be a conflict creating a L3 protocol error. But the more dangerous situation is what happens if another core requests the data.

If another core requests the data it will first check for it in L3, and of course find it there, not knowing that an adjacent core also has the data in its L2. The second core will now pull the data from L3 and place it in its L2 cache but keep in mind that the data is marked as unmodified, while the first core has it marked as modified in its L2.

At this point everything is ok since the data in both L2 caches is identical, but if the second core modifies the page table data that could create a dangerous problem as you end up in a situation where two cores have different data that is expected to be the same. This could either result in a hard lock of the system or even worse, silent data corruption.

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The BIOS fix

The workaround in B2 stepping Phenoms is a BIOS fix that tells the TLB it can't look in the cache for page table entries upon lookup. Obviously this drives memory latencies up significantly as it adds additional memory requests to all page table accesses.

The hardware fix implemented in B3 Phenoms is that whenever a page table entry is modified, it's evicted out of L2 and placed in L3. There's a very minor performance penalty because of this but no where near as bad as the software/BIOS TLB fix mentioned above.

AMD gave us two confirmed situations where the TLB erratum would rear its ugly head in real world usage:

1) Windows Vista 64-bit running SPEC CPU 2006
2) Xen Hypervisor running Windows XP and an unknown configuration of applications

AMD insisted that the TLB erratum was a highly random event that would not occur during normal desktop usage and we've never encountered it during our testing of Phenom. Regardless, the two scenarios listed above aren't that rare and there could be more that trigger the problem, which makes a great case for fixing the problem

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It does sound like a rare occurrance, and a very rare chance of BSOD I could live with, but data corruption isn't something you want to mess with

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Originally posted by sammorris:

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That's a really smart looking case actually, not sure about the giant raised button at the front, but apart from that, it's nice. I especially like the wide use of 200mm fans, the four front USBs, the fact it still has a 3.5" bay, and that it's a raised case with a bottom intake (and with a fan size worth having, take note NZXT!)
Looks like there's ample room for an 11" graphics card in there too.

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Originally posted by sammorris:

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Um, in here?
http://forums.afterdawn.com/thread_view.cfm/16/672592

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Originally posted by bigwill68:

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This looks interesting for tranfer heat faster:)

http://www.thermalright.com/new_a_page/p...er.html

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Originally posted by sammorris:

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At high fan speed (very loud, a 120mm fan at 2600rpm doesn't even bear thinking about) the Zerotherm cools 2ºC better than an Ultra-120 (aluminium) does with a quiet 1200rpm fan. In silent mode, where the cooler generates a similar noise level, it is 5ºC behind, which while not bad, puts it only just ahead of the Noctua NH-U12F. Of course it is still admirable as at this silent speed it outperforms the Freezer 7 Pro by 2 degrees and the Zalman CNPS9700 by 5 degrees, both these coolers at their noisy full fan speeds.
What's quite funny is that all these coolers perform at least 22ºC (Zalman 9700) better than the Intel stock cooler.

Figures from Bit-Tech

Long story short, for the sake of 2.5ºC I'd probably save and get the Freezer 7, and if I wanted awesome cooling performance I'd stick with the cheaper, more manageable Ultra-120A or Ultra-120 Extreme Aluminium.

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At high fan speed (very loud, a 120mm fan at 2600rpm doesn't even bear thinking about) the Zerotherm cools 2ºC better than an Ultra-120 (aluminium) does with a quiet 1200rpm fan.

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