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Unlike generalised CPU's or specialised GPU's, however, the field-programmable grid arrays (FPGAs) used in reconfigurable computing can be programmed with a different instruction set depending on thier use. The announcement that Sony's Playstation 3 will be powered by a processor called the Cell, which incorporates multiple reconfigurable units, has brought the idea into the public eye.

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The Cell, for example, incorporates a control CPU based on a 64-bit PowerPC chip, plus eight FPGAs called synergistic processing units (SPUs). These nine elements talk to each other via a high-speed Element Interconnect Bus.

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It's still unclear exactly what will be inside the Playstation 3. Some have claimed it could incorporate as many as four Cell chips, but most reports give it a single Cell running at 3.2GHz. It will also have just seven of the eight SPUs activated to increase yeild. This allows one faulty SPU core per CPU, so more chips will pass manufacturing tests. Sony claims that the Cell makes the Playstation 3 more powerful than Deep Blue, the supercomputer that beat chess grandmaster Garry Kasparov in 1997.

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i hope the PS3 is showed off at this years E3 more.

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Although FPGA technology has many benefits, there's one destinct drawback. Programming for reconfigurable chips is a lot more complicated. Whereas the fixed set of operations in a regular processor forces programmers to work around its limitations, the total freedom of the FPGA means that code is attempting to hit a constantly moving target.

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Not only does the programmer have to work out the best software routines to complete a task, but also the optimum state for the FPGA. Although the potential speed gains are clearly enormous, getting the combination wrong could have exactly the opposite effect. As we explained earlier, a specialised instruction is only useful for the intended code sequence. Faced with different operations it will either be perilously slow or of no use at all.

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Programming for the FPGA's requires a greater level of expertise and understanding than is currently required in software development. The programmer has to be an inventor of virtual chip microcode, not to mention the software that runs on it as well.

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Now you see where the Sony hype comes from about it being the equivilant to a super computer.

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The CPU, codenamed Xenon, is a customised IBM PowerPC chip running three symmetrical cores at 3.2Ghz with 1MB of Level 2 cache, To make it even faster, each core actually runs two hardware threads, much like a Hyper-Threaded Pentium 4.

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The Xenon works in tandem with the Xenos, the ATI graphics processor and main memory controller. This is an entirely new architecture, understood to have little in common with the new R520 chip. For one thing, the 500MHz GPU contains 10MB of embedded DRAM, which apparently enables the Xenos to perform 4X anti-aliasing on a high-definition 1280 x 720 Progressive scan image. For another, where existing PC graphics parts still split thier pipelines into seperate vertex and pixel shaders, Xenos uses a unified shader architecture with three parallel groups of 16 shader units that can be allocated dynamically where needed. This doesn't quite make the Xenos the equivalent of a 48-pipeline GPU, but it's close.

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